The present invention relates to a power semiconductor device and a manufacturing method thereof, which is provided with a gate-driving element such as a longitudinal MOSFET and an insulated gate bipolar transistor (IGBT) in which a number of transistor cells of a so-called trench structure having a gate electrode formed in a trench formed from the surface of a semiconductor layer. More particularly, the present invention relates to a power gate driving semiconductor device and a manufacturing method thereof, which is allowed to have a reduced on-resistance by increasing the number of transistor cells per unit area so as to provide a great current and can be manufactured through a simple manufacturing process.
Conventionally, with respect to a high-power gate-driving power MOS transistor, a construction in which a great number of transistor cells are formed in parallel with each other to form a matrix format has been adopted so as to provide a greater current. For example, as shown in FIG. 7, a transistor of a planar construction is formed in the following processes: an n-type semiconductor layer (epitaxial growth layer) 21 to be formed into a drain area is epitaxially grown on, for example, an n+-type semiconductor substrate 21a, and p-type impurities are diffused on its surface side so that a p-type body area 22 is formed, and an n+-type source area 23 is formed on the peripheral portion of the body area 22. A gate electrode 25 is formed on the peripheral edge portion of the body area 22 and on the surface side of a semiconductor layer 21 located on the outside thereof through a gate oxide film 24, and a channel region 22a is formed on the peripheral edge portion of the body area. Then, a source electrode (source wiring) 27 is formed to be connected to the source area 23 and the body area 22 by Al, etc., through a contact hole placed in the interlayer insulating film 26, and a drain electrode 28 is formed on the rear face of the semiconductor substrate 21a. 
With respect to a power MOSFET having the trench structure in which gate electrodes are embedded in grooves formed in the semiconductor layer, as shown by an example in FIG. 8, trench are formed in a semiconductor layer 21 in a lattice shape, and after polysilicon to be formed into gate electrodes 25 have been embedded therein, a gate oxide film 24 is formed on the periphery thereof through oxidation, or after the gate oxide film 24 have been formed on the inner surface of the trench, polysilicon to be formed into gate electrodes 25 is embedded therein, so that the gate oxide film 24 and a gate electrode 25 are formed. Then, a p-type channel diffusion area 22 and an n+-type source area 23 are formed around the gate electrode 25, and a channel region 22a is formed in the longitudinal direction. A source electrode 27 is formed so as to make an ohmic contact with the source area 23 and the channel diffusion area 22, and a drain electrode 28 is formed on the rear surface of the semiconductor substrate 21a, in the same manner as FIG. 7.
Here, the planar structure of the gate electrode in these transistors is formed into a desired shape, such as a square, a pentagon or a hexagon. Moreover, in most cases, these transistors are connected to an inductive load such as a motor, and in such a case, when the operation is turned off, an electromotive force tends to be applied thereto in the reverse direction, therefore, in order to prevent the transistor from destruction, as described above, the source electrode 27 is also allowed to contact the channel diffusion area 22 so that a protective diode in the reverse direction is formed between the source and the drain.
In the case of a large-current transistor as described above, it is important to make as many transistors cells as possible in a chip having a fixed size so as to decrease the on-resistance. In order to decrease the on-resistance, it is effective to make the channel width as wide as possible, and in the case of a transistor having the above-mentioned structure, it is preferable to make the total width (the length on the periphery of the gate electrode) of the channel region 22a formed on the periphery of the gate electrode as great as possible.
However, conventionally, in transistors of this type, since the source electrode is made in ohmic-contact with the channel diffusion area on the surface of the semiconductor layer, both of the source area and the channel diffusion area need to be exposed to the surface of the semiconductor layer, and since it is necessary to provide a margin used for a mask-superposing process upon diffusing to form the source area and a margin used for a mask-superposing process between a contact hole and a source area, the size C of the contact hole needs to be set to approximately 2 to 2.5 xcexcm, for example, in the structure shown in FIG. 8, and the cell gap (pitch between the gate electrodes) A is limited to approximately 4.5 to 5 xcexcm. In this case, the width B of the source area is set to approximately 0.8 to 1 xcexcm. For this reason, it is not possible to sufficiently miniaturize the cell and to increase the number of cells, and the resulting problem is that it is not possible to sufficiently reduce the on-resistance.
The present invention has been devised to solve the above-mentioned problems, and its object is to provide a semiconductor device that is provided with an insulated gate-driving element of a trench construction or a planar-type, which reduces the on-resistance by increasing a gate width even with a chip area of the same size to provide a great current.
Another object of the present invention is to provide a manufacturing method of a semiconductor device which, in the case when there is an element which has the source electrode to be made in contact with both of a channel diffusion area and a source area, makes the source electrode in contact with these with a very small area by using a simple process.
Still another object of the present invention is to provide a manufacturing method of a semiconductor device which makes the source electrode in contact with both of the channel diffusion area and the source area while the pitch of the transistor cells is made very small, by allowing the source electrode to contact in a self alignment without the necessity of a mask alignment margin, and which is obtained by using a very small area through a simple process.
The inventors of the present invention have studied hard to provide a semiconductor device which minimizes the on-resistance of an insulation gate type semiconductor to obtain a great current with a small chip size, and have found that, although when, in general, a metal film such as Al is directly formed on the surface of a semiconductor layer as an electrode, it spikes into the semiconductor layer, resulting in a problem such as short-circuiting, a barrier metal layer is normally interposed in between, but the amount of the metal invading into the semiconductor layer due to the spike can be controlled by controlling conditions such as the thickness of the metal film to be formed and the thermal process, and the spiked alloy layer is sufficiently made in ohmic contact with the semiconductor layer.
Even in the case when the source electrode is made in contact with both of the source area and the channel diffusion area, the source area and the channel diffusion area are formed longitudinally so that the source electrode is allowed to spike into the channel diffusion area of the lower layer to provide superior ohmic contacts in both of the layers.
Moreover, by thickly oxidizing the gate electrode surface of the trench construction to provide an insulating film on the surface without forming a contact hole, even when the metal of the source electrode directly formed on the surface is allowed to spike, it is possible to make the metal in ohmic contact with both of the source area and the channel diffusion area longitudinally formed without causing short-circuiting between the gate electrode and the source electrode. Consequently, although a mask needs to be formed upon forming a trench so as to provide the gate electrode, it is possible to carry out a manufacturing process in a self alignment after the trench has been formed, and consequently to eliminate the margin used for the mask adjustment, thus, it becomes possible to provide a semiconductor device having a very small-size chip, and to greatly simplify the manufacturing process.
A semiconductor device in accordance with the present invention, which is provided with an insulated gate-driving element for controlling a channel region interposed between a source area and a drain area by using an insulated gate electrode includes; a semiconductor layer to form a drain area, a channel diffusion area formed on the semiconductor layer, a source area for interposing a part of the channel diffusion area in cooperation with the drain area, a gate electrode that is placed on a channel region which is the part of the channel diffusion through a gate oxide film, a source electrode formed so as to be electrically connected to the source area and channel diffusion area, and a drain electrode formed so as to be electrically connected to the drain area, wherein the source area is formed so that at least a part of the source area places on the channel diffusion area, and the source electrode is formed on a surface of the source area by a metal film, a metal of the source electrode being allowed to spike into the source area and the channel diffusion area to form an alloy layer with the source area and the channel diffusion area, thereby the source electrode being made in ohmic contacts with both of the source area and the channel diffusion area through the alloy layer.
With this arrangement, it becomes possible to eliminate the necessity of a masking process for diffusing the source area, and the alignment margin is required only when a contact hole is formed, and is not required so much. Further, it is not necessary to form contact areas to both of the source area and the channel diffusion area on the surface of the semiconductor layer, and it is only necessary to expose only the source area to the surface, therefore, it is possible to greatly miniaturize the contact hole. Consequently, the pitch of the gate electrodes is greatly narrowed and the number of cells is increased greatly, consequently, it is possible to provide a high-power semiconductor device which has a widened gate electrode, minimizes the on-resistance and provides a greater current.
More specifically, the above-mentioned insulated gate-driving element may be a device having a trench construction in which the gate electrode is formed in the trench of the semiconductor layer and the channel diffusion area and the source area are formed in a longitudinal direction around the trench or a planar-type element in which the gate electrode is formed on the surface of the semiconductor layer through a gate oxide film.
Moreover, with respect to the semiconductor layer, in addition to silicon, silicon carbide, etc. may be used, and in the case of the source electrode made of aluminum, this is readily allowed to form an alloy with silicon or silicon carbide, thereby making it possible to easily form an alloy layer through spiking.
With respect to a specific construction of a gate-driving semiconductor device of the trench construction, it is provided with a trench formed in a first conductivity type semiconductor layer, a gate oxide film formed on the surface inside the trench, a gate electrode embedded into the above-mentioned trench, a second conductivity type channel diffusion area formed on the surface of the semiconductor layer around the gate electrode, a first conductivity type source area further formed on the surface of the channel diffusion area, an insulating film that is thickly formed through oxidation of the gate electrode on the surface side of the gate electrode, a source electrode made of a metal directly formed on the surface of the insulating film and the surface of the source area, an alloy layer that is formed by allowing the metal of the source electrode to spike into the source area and the channel diffusion area, and a drain electrode that is electrically connected to the semiconductor layer.
With this arrangement, the insulating film is thickly formed on the surface side of the gate electrode through oxidation of the gate electrode, therefore, even when an insulating film is not formed on the surface to form a contact hole that exposes the source area, and a source electrode being directly formed on the surface of the semiconductor layer generates spikes through a thermal treatment, no short-circuiting is caused to the gate electrode.
In other words, it is not necessary to form a contact hole by forming an insulating film on the surface of the semiconductor layer, therefore, the source area and the source electrode are formed through self alignment by forming only the gate electrode. Consequently, the margin for a mask alignment is no longer necessary, the pitch (interval) of the transistor cells can be narrowed greatly, and the number of transistor cells per unit area is increased, thus, it becomes possible to reduce the on-resistance, and consequently to provide a high-power MOSFET having a great current.
The gate electrode and the insulating film are formed in such a manner that the surface side of the gate electrode is engraved deeper than the surface of the semiconductor layer, the insulating film is formed through oxidation of the gate electrode with the surface of the insulating film being set virtually in the same level as the surface of the source area, thus, the surface is flattened, the source electrode (source wiring) is also flattened, and the source electrode (Al) is flattened, and uniformed so that it becomes possible to provide a stable spiking process.
The manufacturing method of a semiconductor device in accordance with the present invention includes the steps of; (a) forming a trench in a first conductivity type semiconductor layer serving as a drain area, and forming a gate electrode in the trench through a gate oxide film, (b) successively diffusing a second conductivity type impurity and a first conductivity type impurity on the semiconductor layer so that a channel diffusion area and a source area are formed in a longitudinal direction, (c) forming a source electrode made of a metal on the surface of the source area, (d) carrying out a thermal process to allow the metal of the source electrode to spike into the source area and the channel diffusion area so that an alloy layer for allowing the source electrode to be made in ohmic contact with the source area and the channel diffusion area is formed, and (e) forming a drain electrode that is electrically connected to the first conductivity type semiconductor layer. Here, the order of these respective processes is not particularly limited, and, for example, steps (a) and (b) may be carried out reversely.
This method makes it possible to form the channel diffusion area and the source area completely in the longitudinal direction, and consequently to form a gate-driving semiconductor device of a trench construction with a very small area.
When the formation of the source electrode is carried out after having formed a contact hole in an insulating film formed on the surface of the semiconductor layer in a separate position from the gate oxide film, the channel region is preferably made less susceptible to erosion by the alloy layer.
In another aspect of the manufacturing method of a semiconductor device in accordance with the present invention that relates to a manufacturing method of a gate-driving semiconductor device of a planar type, it includes the steps of (axe2x80x2) forming a gate electrode on the surface of a first conductivity type semiconductor layer serving as a drain area, (bxe2x80x2) successively diffusing a second conductivity type impurity and a first conductivity type impurity on the semiconductor layer around the gate electrode so that a channel diffusion area and a source area are formed so as to form a channel region under the gate electrode, (c) forming a source electrode made of a metal on the surface of the source area, (d) carrying out a thermal process to allow the metal of the source electrode to spike into the source area and the channel diffusion area so that an alloy layer for allowing the source electrode to be made in ohmic contact with the source area and the channel diffusion area is formed, and (e) forming a drain electrode that is electrically connected to the first conductivity type semiconductor layer.
With this method also, it is not necessary to expose the channel diffusion area to the surface of the semiconductor layer so as to make the channel diffusion area in contact with the source electrode, thus, it is possible to greatly minimize the cell pitch, to widen the gate width by increasing the number of cells, and consequently to provide a great current.
In still another aspect of the manufacturing method of a semiconductor device in accordance with the present invention, it includes the steps of (a) forming a trench in a first conductivity type semiconductor layer serving as a drain area, and forming a gate electrode in the trench through a gate oxide film, (bxe2x80x3) successively diffusing a second conductivity type impurity and a first conductivity type impurity on the semiconductor layer in any one of the steps so that a channel diffusion area and a source area are formed in a longitudinal direction around the gate electrode, (f) forming a thick insulating film by oxidizing the surface of the gate electrode, as well as exposing the surface of the source area, (cxe2x80x2) forming a source electrode made of a metal on the surface of the insulating film formed on the exposed surface of the source area and the gate electrode, (d) carrying out a thermal process to allow the metal of the source electrode to spike into the source area and the channel diffusion area so that an alloy layer for allowing the source electrode to be made in ohmic contact with the source area and the channel diffusion area is formed, and (e) forming a drain electrode that is electrically connected to the first conductivity type semiconductor layer.
With this arrangement, it is not necessary to form a contact hole by forming an insulating film on the surface of the semiconductor layer and the source electrode is formed through self alignment, therefore, the gap of the transistor cells can be narrowed greatly and the on-resistance can be reduced, thereby making it possible to greatly simplify the manufacturing process, and also to manufacture the device at low costs.
Prior to the formation of the insulating film on the surface side of the gate electrode, the surface of the gate electrode is engraved deeper than the surface of the semiconductor layer through etching so that the insulating film is formed so as to set the surface of the insulating film formed through the step (f) virtually in the same level as the surface of the source area exposed through the step (f), thus, the surface is flattened although it still has a trench structure, and it becomes possible to provide a semiconductor device having a power MOSFET with a flat surface.
In another method, prior to the formation of the insulating film on the surface side of the gate electrode, an oxidation preventive film is formed on the surface of the semiconductor layer around the gate electrode so as to oxidize only the surface of the gate electrode, thus, it becomes possible to form a thick oxidized film only on the gate electrode by oxidizing only the surface of the gate electrode without the necessity of an etch back process using RIE, etc.